Advance Digital System Design with FPGAs

Aug. 2020 – Oct. 2020

  • Using Verilog on a Xilinx FPGA to realize sensor reading through SPI, 7-segment display control, and VGA display output.
  • Every module is tested using simulation in Vivado by creating external scripts including Verilog model of external components.
  • Converted an existing ASCII font library in VHDL into a memory file for initializing a ROM which provides font data.
  • Simplified the graphical section by segmenting each chunk of rendering into submodules through masking the pixel indexing signals.

Picture of the VGA monitor showing the FPGA output